This is page has been quickly thrown together as a place to stick some pictures and descriptions of this 10 GHz transverter and other 10 GHz-related activity.
The signal flow is like this (See the block diagram to the right):
Since the "benchtop and clipleads" picture was taken, I screwed the various modules to a piece of plywood: While not elegant, it allows the unit to be transported and easily worked on.
Note: The circuits depicted are drawn as-built. It is likely that further improvement could be made in terms of optimizing performance and/or simplification. These diagrams are provided simply to show one possible approach to solving the technical problems presented and are, in no way, intended to represent the ideal or state-of-the-art.
These schematics are hand-drawn and then scanned. While reasonable efforts have been made to assure accuracy and legibility, it's possible that errors may be present. If you have any questions, please feel free to send an email.
Note that not all bypass capacitors (on ICs, etc.) are shown
on the schematic: These capacitors (0.01 or 0.1 uf) are
liberally sprinkled about the various circuits to provide
bypassing to prevent unwanted cross-coupling of energy on power
Since drawing the schematics, a few changes have been made -
not all of which have been mentioned on these web pages.
NOTE about the "brick" power supply:
Due to a mishap, I managed to blow up my original "brick" oscillator. Fortunately, I was able to procure another "brick" of the same manufacture and simply fit the multiplier module to it, retuning the main oscillator. Instead of requiring +24 volts, it operated from -20 volts so I had to constructed a -20 volt power converter for it. At the moment I don't have a diagram of that converter on this web page, but that can be supplied upon request.
Schematic- Power converter: This is a very simple boost-type voltage converter using the ubiquitous TL494 PWM switching controller IC - the same IC seemingly found in almost every PC power supply ever made. This converter operates with an input voltage in the range of 8 to 16 volts (the upper end mainly limited by the voltage rating of the power supply bypass capacitors) and can supply at least 1 amp at 28 volts.
Operation: The input voltage is filtered and bypassed, using low-ESR electrolytic capacitors and a series choke. Other than providing a low impedance voltage source for the switcher, this filtering prevents switching frequency components (22 kHz and harmonics thereof) from being superimposed on the power supply line, possibly working their way into other circuits.
The TL494 consists of an oscillator, a voltage reference, some
comparators, and some output switching logic. The square wave
output of the oscillator is fed to the chip's driver transistors
(through the switching logic) which are, in this case, configured
as a totem-pole driver to a power MOSFET transistor, a MT5N05EL
which is a generic 60 watt, 15 amp, 50 volt device (with a 0.14
ohm ON resistance with 5 volts on the gate) that I pulled out of
my parts bin: This transistor is nothing special except that
I bought several rails for nearly nothing at a hamfest swapmeet
several years ago and it is likely that a beefier transistor (with
lower ON resistance) might improve efficiency somewhat. When
the transistor is on, current through the 20 uH inductor causes
energy to be stored magnetically: When the transistor is
switched off, this energy is released as the field collapses and
the resultant current flows through the diode (a high-speed
diode pulled from a defunct computer power supply - a "normal"
diode like a 1N4001 will not work well!) and into
the output capacitors.
The TL494's internal 5 volt reference is compared with a resistively-divided voltage from the output capacitors and this divisor ratio (in this case, 10k and 47k) is used to set the output voltage. When the output voltage exceeds the threshold, the oscillator's output is gated off, shutting off drive to the switching transistor. In this application, a portion of the "feedback" signal (output line from the voltage comparators) is fed into the inverting input of the comparator: This feedback allows duty-cycle modulation of the drive signal from the oscillator, allowing for smoother, more-responsive regulation. Without this feedback, the converter would operated in a "discontinuous" mode where the drive was abruptly started and stopped. In applications (such as this) that could be potentially sensitive to power supply fluctuations, the discontinuous mode of operation may pose stability/purity problems.
The output from the storage capacitors goes through a 80 uH choke followed by more filtering. This filtering, too, is important to prevent bleedthrough of the switching signal through the output voltage and because the switching currents present in the 20 uH inductor are mostly removed by the filter capacitors, the magnetic characteristics of this choke aren't as critical and almost all of the heating will be due to IR losses. Note that the schematic indicates the use of a "common-point ground": When using a switching supply with high currents, good-quality capacitors, a robust ground plane, and good wiring techniques are required to prevent the energy from the switching frequency getting into everything and one of the most important of these techniques is the use of a common-point ground - a single location where all high-current conductors (and components) tie together. Were this not done, I/R losses would impose the switching frequency on otherwise-unrelated components, reducing the effectiveness of output filtering. Note that the other chokes, because they aren't exposed to high switching currents, need not be as "heavy duty" as the 20 uH choke used in the voltage converter.
It's worth mentioning that low-ESR capacitors are absolutely essential in this application where noted!
While every low-ESR capacitor that I have seen has stamped on it a temperature rating of 105 degrees C, not every 105 C capacitor is of the low-ESR version! Often, low-ESR capacitors may be found in switching supplies - but be absolutely certain that the capacitor itself isn't bad and wasn't the reason why the supply itself was junked. How important is the use of a low-ESR capacitor? Just for grins, I put a "normal" 470 uF electrolytic capacitor in place the two paralleled 220 uF units: The 470 uF capacitor immediately got too hot to touch and the efficiency of the voltage converter plummeted. Had I left the unit running, the capacitor would certainly have vented or simply blown up! In contrast, the two low ESR 220 uF units barely run warmer than ambient temperature. In the other positions calling for low-ESR capacitors, the AC current isn't nearly as high, but a "normal" capacitor doesn't work there, either because they have high enough impedance at the switching frequency that they do not effectively filter out the residual ripple.
The two devices that require this upconverted voltage (the 5 MHz ovenized oscillator - which was replaced with an external reference and the "brick" oscillator) actually operate at 24 volts. To provide this voltage - as well as to further improve power supply cleanliness and stability, each of these other devices has its own 7824 3-terminal regulator. While the addition of a linear regulator decreases overall efficiency somewhat, the relatively small input/output differential voltage makes these losses fairly small.
To conserve power, I added some power switches to allow me to turn off the "Brick" oscillator and the VCXO module and lock unit and all that remained powered up was the 5 MHz ovenized oscillator. Being able to power down these other circuits slashes the current consumption but allows the most critical component of the system - the 5 MHz reference - to remain warm and stable. The "Brick" and the lock unit stabilize within a second or two of being powered up.
Schematic- VCXO Module:
The heart of this module is the 18.4 MHz oscillator. A fundamental-mode oscillator was used (rather than starting out with an overtone oscillator at 110.4 MHz) for two important reasons:
This oscillator is the well-known "Butler" type. While slightly more complex than other types this oscillator was chosen because it is cleaner and more stable than many others. The crystal is placed in the feedback path of two amplifier stages, and with the relatively low crystal drive, internal heating is minimized, aiding stability. Also, with the crystal in series with the signal path (and with both amplifiers operating well within their linear regions) the output signal is effectively filtered through the crystal itself. Electronic tuning is accomplished by using a varactor diode (an NTE614) in the crystal's feedback path allowing about 1 kHz of "warpage" at 18.4 MHz - more than enough range to accommodate thermal/age-related drift. Note that in low phase-noise oscillators, it is common to use back-to-back varactor diodes to minimize incidental phase modulation: I may make this change at some point.
Also attached to the tuning line is a very simple loop filter. The output of the phase/frequency detector (see below) is essentially a square wave with a varying duty cycle (at least when at/near lock) and this filter integrates the voltage to a DC level proportional to the duty cycle. A simple transistor "inverter" is used to increase the voltage range from the phase/frequency detector: The output swing voltage of the phase/frequency detector, after filtering, is from approximately 1 volt to 4 volts, but the transistor, being operated from the 9 volt supply, extends this to about 8 volts on the high end, increasing the range of electronic tuning. Of course, the output of the phase/frequency detector must be "pre-inverted" to accommodate the inversion performed by this transistor. The loop filter shown is quite minimal: In the future, this will be improved to reduce the amplitude of the reference sidebands.
Following the 18.4 MHz oscillator is a FET-based buffer: This provides minimal loading of the oscillator and drives a class-C tripler that multiplies the 18.4 MHz crystal frequency to 55.2 MHz. A two-stage L/C filter isolates the 55.2 MHz component, removing most of the original 18.4 MHz energy.
Following the tripler is a frequency doubler that produces the 110.4 MHz signal. It, too, has a two-stage L/C filter that removes 18.4 MHz and 55.2 MHz energy and the output from this filter is passed to an additional stage (also with filtering) that further amplifies/cleans up this signal.
The output from the 110.4 MHz amplifier is sent to two places: One of these is a 110.4 MHz buffer comprised of an emitter-follower. It is the output of this stage that is fed to the "brick" oscillator that produces the 9936 MHz local oscillator signal.
The 110.4 MHz output signal is also sent to another, identical emitter-follower amplifier that buffers the 110.4 MHz signal that is then applied to the base of the harmonic mixer transistor. 10 MHz energy (amplified/filtered from the master reference) is fed into the emitter of this stage and the collector, connected through a 455 kHz IF transformer, is used to extract and filter the minute amount of 400 kHz energy resulting from the mix between the 11th harmonic of the 10 MHz reference (110 MHz) and the 110.4 MHz signal.
Two stages of filtering clean up the resulting 400 kHz signal and it is amplified by a FET and buffered by a bipolar transistor stage. The output of this bipolar stage is then lowpass filtered to remove traces of higher-frequency components and made available to the lock unit.
Schematic- Lock Unit:
Both the 400 kHz signal from the harmonic mixer and the 10 MHz reference pass through similar amplifiers that convert their respective inputs to logic-level signal suitable for driving digital dividers.
The outputs of these amplifiers are applied to XOR gates for buffering: U1A for the 10 MHz reference signal, U1C for the 400 kHz output from the harmonic mixer.
The 10 MHz output from U1A is passed to U2 and U3, each of which is wired as a divide-by-5 counter, and the final result is a 400 kHz signal based on the stable 10 MHz reference oscillator.
The two 400 kHz signals (one from the reference and the other from the harmonic mixer) go to the two inputs of the phase/frequency detector. Flip-flop counter U4A and U4B divide each of the signals by two, ensuring a perfect square wave from each source and these outputs are sent into U1D, an XOR gate. If the frequencies are very close to each other, the output of U1D is a square wave with a duty cycle that varies in a way proportional to the phase difference.
The more different they get from each other, however, U5A and U5B begin to put clock glitches on the output waveform. The ultimate result is that if the input frequency is higher than the reference frequency, the output from U6B (the combined output of the XOR gate and U5) will spend the majority of its time low - and vice-versa if the input frequency is lower than the reference frequency, allowing this circuit to provide PLL action over an extremely wide tuning range (unlike a simple XOR-based circuit.) The action of the loop filter (on the VXCO module) integrates these clock glitches to a pure DC voltage for frequency control. U6C is simply a logic inverter to accommodate the presence of the inverter/amplifier transistor at the loop filter on the VCXO board.
This sort of phase/frequency detector is similar to that found in the Analog Devices AD9901 and it has the advantage of not having the "deadband" problem that the phase/frequency detector used in the 4046: In this condition, when the PLL is locked, the 4046's phase/frequency detector goes into a "tri-state" condition and when a frequency correction is needed, pulses (either high or low, depending on what is needed to provide the frequency correction) are output to correct the tuning. The problem is that these correction pulses may occur infrequently enough that their frequency components are below that removed by the loop filter and the result is that "bouncing" can occur and low frequency noise may be introduced into the system. In the phase/frequency detector shown, the XOR gate is doing most of the work when in lock and it is continually putting out a square wave of varying duty cycle and can never have any spectral components below this frequency (aside from the phase/frequency corrections, of course.)
Note that in this application, a simple XOR-gate phase/frequency
detector would probably have sufficed, but I wanted to try this
circuit to see how well it worked.
There is a lot of room for improvement. A few things that come to mind immediately are:
Go to the KA7OEI main page.