TEXT REV: 1.4, 20020121 (SUPERSEDES VER 1.3, 980720) Revision description as of ver 1.4: - Original HP-GL and PCL graphics have been converted to bitmap .GIF. - Drawings have been corrected as per original errata sheet. There are no known errors on the schematics. If you find anything that you believe to be in error, please report it via the email address at the bottom of this document. Description of the Utah T1 Modem General Description This modem is intended for T1 (and possibly E1) data rates on full-duplex links. This modem produces baseband modulation and expects a demodulated baseband input from a demodulator. Because the clock recovery is based on a VCXO (Voltage Controlled Xtal Oscillator) its lock-up time is as long as a second. This is acceptable on a full-duplex link since the received data stream is continuous. This modem supplies both the transmit and receive data clocks at the frequency equal to the baud rate. The data transmitted by this modem is scrambled according to the X = 1 + X(E-5) + X(E-17); that is, the transmitted data is XORed with the data transmitted 5 and 17 bits ago. The receiver employs a matching descrambler. This modem set is *NOT* really a T1 modem in that it does not do the "T1-like things" such as send/receive bipolar data, AMI, B8ZS, RBS, etc. The "T1" designation is soley indicative of its speed and not the data format. Useage of this modem and the work herein: Unless you are an amateur radio operator with priviledges commensurate to such operation, this modem will likely be of absolutely *NO* use to you! It has in no way been designed to be useable as an FCC Part 15 building-block and is not suitable for any sort of long-distance communications under that part. In the U.S. its use, as designed, is limited to the bands 33cm and higher. The use and utilizations of the various apparatus described in and referred to by this document is permitted so long as it is done legally. The user is free (and encourage) to make modifications and improvements provided that such improvements be forwarded to the author so that they can be shared with others in order to advance the state-of-the-art in communications. No warranties are expressed or implied, and your mileage may vary. Please see the paragraphs at the end of this document that pretty- much reiterate this spiel... Circuit Descriptions: The Demodulator (Drawing reference: Utah T1 Modem Clock Recovery/Data Demodulator, Rev. E.1 20020131) Clock recovery circuit: The heart of this circuit is the 24 MHz VCXO. This uses a fundamental mode crystal oscillator operating at 16 times the baud rate. The hyperabrupt varactor diode (D1) is used for tuning the VCXO. Inductor L1 increases the "warping" range of the oscillator and allows center frequency adjustment. U2, a 74HC4040 12 stage binary ripple counter, provides clocking and timing for the rest of the circuit. With the parts shown the VCXO range is approximately 8 KHz (at 24 MHz) for a varactor voltage range of 1.5 to 11.25 volts using the NTE618. The best choice of varactors for this circuit is the MVAM1108, but the NTE618 is commonly available from many parts-supply houses (the prototypes use NTE618's.) The biasing resistor at U1D (R36) centers the waveform from the oscillator at the schmidt window. The clock recovery obtains its data clock information from a "Raw Data Input." This signal is derived from the received analog signal (from the demodulator) and comparing it with a derived slicing level. In this case, it comes from the "data" output of an MC13055 FSK receiver chip. This "Raw Data" signal is buffered by U1A, a shmidt inverter, and all transitions are converted to pulsed by XOR gate U3A and buffered by U3B. The rising edges, which are co-incident with level transitions, strobe U4B high. On the next rising edge of the 24 MHz clock (16Fclk) U4A latches the high level from U4B. The NEXT rising edge of 16Fclk latches the high level from U4A into U5B. The Q-NOT output of U5B then resets both U4B and U4A. The result is a pulse generated by U4A that has the width of a period of 16Fclk and occurs during an interval beginning as early as one 16Fclk period after the data transition (at the soonest) and as late as two 16Fclk periods after the transition. This reset pulse is guaranteed to be of a consistent width and it is applied to the RESET pin of U6, a 74HC4040. This counter is clocked by 16Fclk and the result is that U6's zero count is synchronized with the transitions of the "Raw Data" input. Because U4B, U4A, and U5B provide a reset pulse to U6 that has a delay of approximately 16Fclk, U4A and U9A are used to delay the 1.5 MHz clock line (Delayed Fclk) by approximately that much. This is done to assure that the Fclk signal is in good synchronization with the transitions of the "Raw Data" input. The "synchronized clock" from U6 is compared to the delayed 1.5 MHz VCXO-derived clock (Delayed Fclk) at U7, a 74HC4046. Phase comparator II, an edged-triggered phase/frequency comparator, is used to determine the phase/frequency difference between the "synchronized clock" from U6 and the VCXO. The output is filtered somewhat by R9 and C7 and applied to U8A and its surrounding components, an integrator/loop filter. The component values shown result in a fairly slow lock-up time (as long as a second or so) but they are critically damped. While the lock-up time could probably be reduced by perhaps as much as a factor of 20 the long time constant improves the noise immunity of the system. R11 counteracts the tendency of this type of phase/frequency detector to "jitter" or "bounce" when it is in or near a lock condition and "pulls" it to one edge of the possible "bounce" range. Since this circuit is followed by an outboard integrator, the effect of R11 is quite consistent throughout the lock range of the circuit. Upon testing of the clock recovery circuit it was noted that it exhibited quite a bit of hysteresis with respect to the quality of signal at the instant it lost lock, and the quality of signal needed to re-establish lock. It was noted that even at the better signal quality (the one required to regain lock to the signal) was too poor to recover data with a reasonably low BER. NOTE: Under in-lock conditions the zero-crossing of the input analog signal coincides with the RISING edge of Fclk! Integrate-and-Dump Demodulator: The integrate-and-dump data filter synchronously recovers the data from the analog signal input. To do this it requires a slicing level (which is buffered and filtered by U8B and C15) from an external source. This slicing level is simply a voltage halfway between the positive and negative peaks of the analog signal input. Note: with the prototypes, there was no noted tendency for U8B to oscillate with the capacitor attached directly to its output. If it *does* oscillate, it is important that the series resistor added (between U8B and C15) be as low a value as possible to guarantee stability! C15 is necessary because the back-to-back diodes on the inputs of U12 and U13 go into conduction during the integrate cycles and drag the slicing level around. U1B, U11A, U11C derive the sequencing for the integrate and dump filters. U11B is used to derive the signal to latch the data into U9B at the end of the integration period. To ease timing constraints, two separate integrate-and-dump channels are used. While one channel is integrating the input voltage, that channel's analog switch (U10B or U10A) is enabled. The other channel's comparator is enabled and spends the first half of that period allowing the comparator to settle. At the end of the first half of that period, that comparator's data output is latched into U9B and the dump switch for that channel's integrator (U10C or U10D) are enabled for the last half of that period. U14 and U15 are LM311-type integrators and these have the feature of having open- collector outputs allowing for easy logic level conversion as well as wire-ORing of their outputs. This is handy since the comparators also have "strobe" inputs (driven by transistors Q7 and Q8) for enabling/disabling them during their appropriate periods. Transistors Q3 through Q6 are logic level converters for the 12 volt level required by U10, a 4066. HEXFETs were chosen because a simple bipolar circuit could not come close to providing acceptably fast risetimes. The 560 ohm pullup resistors result in risetimes of approximately 40 nanoseconds which is more than adequate for this task. It may be possible to raise this value to 1k (about 80 ns risetime) in the interest of power savings. If this modem is adapted for a lower baud rate then higher values would certainly be appropriate. Descrambler: The descrambler is a fairly simple circuit that simply uses U16A (a 74HC74,) U17 and U18 (74HC164's) as a 17 bit shift register. Gates U3D and U3C XOR the incoming data with the data that was received 5 and 17 bit periods ago. U16B simply latches the data. There are a variety of jumpers: JMP1 allows the user to select between "Raw Data" and data demodulated by the Integrate- and-Dump demodulators. JMP2 is used to select the sense of the recovered receiver clock with respect to the data (i.e. new data on rising or falling edge of the clock) and JMP3 is used to provide a selectable data polarity. This can be useful for NRZ encoding where data polarity is important. Circuit Descriptions: The Transmitter (Drawing reference: Utah T1 Modem Transmit Clock/Scrambler/Data Filter, Rev. E.1 20020131) The transmitter's master clock is a 24 MHz fundamental-mode crystal oscillator that is suspiciously similar to the one in the receiver. Inductor L2 is used to lower the oscillator frequency slightly and allow frequency tuning to match the center of the VCXO frequency range of the receiver at the opposite end of the link. U19 a 74HC4060, divides this down to the 1.5 MHz bit-rate clock. U23C buffers the input data, providing a means to optionally invert it. This data is latched by U20B which puts that data into the scrambler consisting of U23B, U23A, U20A, U21, and U22. This scrambler works much like the descrambler used in the reciever, so there! The scrambled bit stream is fed to U24, a 4049 (the unbuffered "U" version is preferred) or a 74HC4049. All sections of this inverter are paralleled to provide the lowest drive impedance and output transconductance variations. The output impedance of this is on the order of a few tens of ohms. R30 sets the input impedance of the filter consisting of C20, L3, and C21. The data filter is a 3rd order maximally-flat Bessel lowpass filter with a 3db cutoff of 798 KHz. This filter is based on an article by G3RUH and it provides a very clean "eye" pattern and is simple and effective. Note that the source and load impedance of the filter is expected to be 220 ohms. With this in mind, resistors R31 and R32 provide resistive impedance conversion, provide a 220 ohm load, and can properly source a 75 ohm load. The R31/R32 combination introduce approximately 10db of attenuation. It must be mentioned that if the filter is sourced/loaded with OTHER than 220 ohms, significant eye-pattern distortion will result. Jumper JMP4 is used to select the data sense of the transmitter. Putting a jumper across JMP4 causes the data to be non-inverted by U23C. JMP5 can be opened or closed to select whether the data source will clock data in on the rising or falling edge of the clock. Comments on the circuits: - The 24 MHz clock of the transmit and corresponding receive modems (at opposite ends of the links) must be aligned with each other. Initially, the slug of L1 in the receiver is set approximately 3/4 of the way into the coil. L2 in the corresponding transmitter (which might be miles away!) is adjusted for approximately 6 volts at the junction of U8A, R1, and C3. If proper adjustment results in the slug in either L1 or L2 being near an extreme, some iterative adjustments may be required to provide suitable adjustment range. This sort of adjustment should be performed, preferably, when the transmit modem and its corresponding receive modem are conveniently proximate to each other. - Inductors L1 and L2 are identical but have not been measured. They are slug-tuned inductors and are probably in the area of 500 nH. The number of turns on the forms was experimentally derived to yield a generous VCXO range and a large margin of oscillator reliability/stability. - It is possible that the delay circuits consisting of U4/U5B and U4A/U9A could be replaced with 74HC123's. While this would allow precise adjustment of delays, such small delays can be difficult to maintain accurately over large temperature ranges. Also, a non-synchronous reset of U6 can introduce another source of jitter. 74HC74's are cheaper, anyway... - The precise synchronization of the recovered clock is dependant on the delay caused by U4A and U9A. The RISING edge of the Fclk line is precisely synchronized with the "center" zero-crossing portion of the eye pattern of the received data. The configuration of U4A and U9A are set for use with demodulator being an MC13055 and the "raw data" stream coming from the "data" output of that device. (Refer to the description of the demodulator circuit.) If another arrangement is used it might be necessary to experiment with the positions of the CLK inputs of U4A and U9A on the outputs of U2. - During design/construction of the prototype I tried driving the transmit data filter with U22 directly but its turn-on versus turn-off resistance was non-symmetrical. Also, such parameters are prone to vary with temperature and chip-to-chip variations. A totem-pole driver was also tried but it worked poorly with a simple circuit. - NONE of the schematics show all of the bypass capacitors needed in the circuits. - The 5 to 12 volt logic conversions done by the HEXFET devices are simple, but they consume a fair amount of current. A Motorola CD40106 might work, but the specs indicate that it may be too slow. - The prototype link uses NRZ coding as opposed to a differential coding scheme (such as NRZI.) Briefly, NRZ uses absolute 0-1 data bits as transitions whereas the other uses a TRANSITION or NON- TRANSITION levels to signify a 0 or a 1. Because of the scrambler, the coding scheme chosen has no real effect on the modems themselves except that with NRZ, there must be NO data inversion through the system. This would occur if either a jumper was set incorrectly (JMP3 or JMP4) or if the receiver used high- side local oscillator injection. Description of the IF Demodulator/Slicing Level Generator. (Drawing reference: Utah T1 Modem Receive Demod/Amp/Slicing Level Gen., Rev. E.1 20020131) This circuit uses an MC13055 wideband FSK chip as the amplifier, limiter, quadrature detector, signal strength detector, and "Raw Data" demodulator for the clock recovery circuit. The 70 MHz input is very broadly filtered (tight filtering is neither necessary or desired at this particular point in the signal path!) and a loaded parallel-tuned circuit serves as the quadrature network on pins 8 and 9. The discriminator on this chip provides a differential output that is at a fairly low level. This signal is differentially amplified by an NE592N8 to a level determined by the gain control. Note the presence of the offset control indirectly connected to pins 10 and 11 of the MC13055 through the 3.9k resistors. This allows biasing of the differential output to be within the input voltage range of the NE592N8. Under no-signal conditions, this should be adjusted so that the averaged voltage on pins 4 and 5 of the NE592N8 is half of the supply voltage. The signal amplified by the NE592N8 is sent, in part, to the MC13055's data comparator. The 0.015 uf capacitor provides a floating slicing level and the 3.3k resistors limit the current into the comparator (which has back-to-back diodes across its input) to reduce loading of the amplifier. It should be noted that the pull-up resistor required for this open-collector output is located at the input of the clock recovery circuit itself (i.e. R8). One of the outputs of the NE592N8 is sent to a unity-gain op- amp (either an LM318 or an NE5534) to provide buffering and adjustment of the center voltage. This offset is adjusted to set the center voltage of this output to half the supply voltage. This analog signal is applied to the integrate-and-dump filters. Don't adjust this until you have first adjusted the one on the input side of the NE592N8. The slicing level is obtained by determining the peak positive and negative voltages of the analog data output (with respect to the "center" voltage,) buffering these voltages, and then averaging the two. The 5k pot across the outputs of these buffers allow fine adjustment to compensate for various offsets. The signal strength is available as a current (to ground) on pin 12. A typical value for this resistor might be 3.3k. It should be noted that the gain control of the NE592 should be set so that the output signal is approximately 1.5 volts peak- to-peak maximum. Also, DO NOT substitute a '733 for an NE592 because the '733 CANNOT be adjusted for a voltage gain of less than approximately 10! It should be noted that the cross- reference for the NE592 in most replacement semiconductor books mistakenly refers to a '733 as the equivalent of an NE592. Comments on the circuit: - Note the word "Preliminary" on the drawing. It is there for a good reason! This circuit has been built and tested, but no part designations have been given since it is expected that a few more pieces of the circuit (i.e. voltage amplifier for the signal strength output, etc.) will be added. - The differential voltage swing of the demodulated output of the MC13055 is on the order of 300 millivolts for approximately 1.2 MHz deviation. If taken single-ended, this is reduced to half. Since these outputs are current sources, the resistors could be increased in value to increase the voltage swing but that would reduce the slew rate of the output. A differential amplifier preserves the differential voltage swing and noise-immunity of the demodulator and allows for a single-ended output with gain adjustment. Because of the limited common-mode voltage range of the input of the NE592, the pot (indirectly at pins 10 and 11) allow adjustment of the voltage range of this point. - While the slicing level could be derived with a simple low-pass type DC averaging filter, those types of filters can be upset by asymmetry in the received signal. This could be caused by a DC "telegraphic bias" in the data stream (which should be prevented by the data scrambler,) a mis-tuning, or distortion of the received signal caused by multipath. A slicing detector that takes the average of both the positive and negative peaks of the signal is less affected by such distortion. - The "fine-tuning" adjustment on the output of the slicing level generator is adjusted for lowest BER under noisy signal conditions. This is best left as an in-situ adjustment with deliberately introduced noise. - No attempt has yet been made to optimize the time constants of the slicing level detectors. GENERAL COMMENTS: - This circuit, as designed, should be capable of supporting bitrates to just over 2 megabaud provided that various components are changed (i.e. integrate-and-dump capacitors/resistors.) Above that rate, some redesign will probably be necessary. With the current design using a crystal oscillator operating at 16 times the data rate it should be kept in mind that fundamental-mode crystals that operate above 30 MHz are difficult to obtain. It may be possible to re-wire U2, U6, and U19 for an X8 oversampling rather than an X16 oversampling and still have acceptable loop characteristics. - It hasn't been tried yet, but it should be possible to use this circuit as part of a Gunn-Diode transceiver based full-duplex data link. To do this, it is suggested that each direction have a slightly different bit rate (i.e. 24 MHz clock = 1.5 mbaud in one direction, 25 MHz clock = 1.5625 mbaud in the other) to keep the each end from ever locking onto its own data clock. Then, using a derivation of the Glenn Elmore 10 GHz megabit data link by using the RF section and substituting the slicing level generator, the differential amplifier section, raw-data recovery circuit consisting of the NE592 and the resistors/capacitors on pins 14 and 15 of the MC13055 of the above circuit. Then, using a high- speed op-amp (such as the LM318 or the NE5534) feed an "anti- modulating" signal into the second LO of the N6GN circuit. This signal would be derived from the same signal that would be modulating the transmitter. It may be necessary to invert that signal and adjust its amplitude in order to best cancel the transmitted data that would otherwise be superimposed on the received signal. - On the receiver, U10, the 4066, another 4066 was "piggybacked" to lower the "ON" resistance of the switch. At 12 volts, there appeared to be plenty of margin for proper operation, but heck, 4066's are cheap, and doing that is easy. Sure, a 74HC4066 could be used, but if that were done, the voltage would have to be limited to an absolute maximum of 10 volts on the analog section. If this is done, be sure to adjust the 'midpoint' of the analog input voltage appropriately. - There have been some comments concerning the "slicing level" detector that is employed. As you can see, it takes an average of the positive and negative extremems of the incoming analog signal and "averages" them. Comments on this circuit mention that this scheme is wildly affected by noise and that it is needlessly more complicated than a simple "lowpass-type" slicing level derivation might be. In "defense" if this circuit I might point out that it is *not* a peak- level detector for either the positive or negative side (i.e. a single "burst" in either polarity will *not* affect the overall level and in tests thusfar, it seems to track the signal very well under induced noise and eye-pattern distortion conditions. - Current work on this modem involves a design of a new "input" board. You noticed that the current "preliminary" input board requires a 70 MHz IF signal. The board then demodulates, and then amplifies and provides a higher-level baseband signal (a volt or so Peak-to-peak) as well as deriving the slicing voltage and a "raw data" signal for data clock recovery. The "newer" version will simply take baseband input and produce those three sigals. This *greatly* simplifies testing of the modem in that it allows baseband loopbacks to be performed. Also, it allows use of a baseband demodulator in an existing receiver, should it be available. DWG REFS: T1MDMCD REV. E.1 (20020131) (FILE: T1MDMCDD.GIF) T1MDMTX REV. E.1 (20020131) (FILE: T1MDMTXD.GIF) T1MDMRX REV. E.1 (20020131) (FILE: T1MDMRXD.GIF) *** CORRECTIONS ON DRAWINGS: No errors are current known on the current (Rev. E.1) drawings. If you find something that you believe to be in error, please report it to the email address at the bottom of the page. IMPORTANT, PLEASE READ!!! The circuits described and contained in the accompanying drawings are preliminary designs. The schematics and descriptions are believed to be accurate and represent actual tested and working circuits. However, as of the time of this writing, thorough field tests have NOT been performed and thus, changes and/or modifications to optimize performance will probably be required! Others are free to copy and use these circuits for non- commercial use provided that credit is given to the author/designer of these circuits (i.e. Clint Turner, KA7OEI.) Also, it is asked (REQUESTED!) that any comments, modifications, and/or constructive criticisms be forwarded to the author/designer! Before you ask, printed circuit board layouts are ***NOT*** available at the time of writing! I do NOT plan to produce anything like that until further field-testing is completed. However, if you are good at that sort of thing, be my guest - all I ask is that you make your designs available so that they may be shared with others. Acknowledgements: I would like to thank the following people for their contribution and ideas: Gordon Smith K7HFV, Marvin Match KA7TPH, Randy Lawrence KG7GI, Glenn Elmore N6GN, Tom Clark W3IWI. Clint Turner, KA7OEI Internet: ka7oei@arrl.net Note: Telephone numbers/addresses on previous versions of this document are no longer current. Please direct any correspondance to the email address above.