Programming the
Osram Pictiva OLED display
(Specifically, the OS128064PK16MY0A01 128x64 serial display)

Disclaimer - please read!:

Additional information about programming Pictiva displays:

More recently, Osram has published information pertaining to the programming of the Pictiva displays - much of which makes the information presented here redundant.  At the time of this writing, this information may be found via links at this urlNote:  This URL has occasionally changed so let me know if it stops working - and what the new URL is.  The relevant information for this display is that for the "4-bit" display - that is, those that use 4 bits to represent each pixel.  (No, it has nothing to do with the bit-width of the interface.)

The electrical interface:

This display is designed for interface with 2.7-3.3 volt logic and does not appear to be "5 volt tolerant."  When the serial interface is used with 5 volt logic, one-way communications is all that is required and something as simple as a 74HC4050 or even resistor-zener voltage limiting could be used to provide logic level conversion.

Symbol Description
1 CS1B Chip Select CS# Chip Select   10 D3 D3 NC No
2 RSTB Reset RST# Reset   11 D4 D4 NC No
3 C86 Par. Interface
  12 D5 D5 NC No
4 RS (A0) Data/Command D/C# Data/Command   13 D6 D6 NC No
5 RW-WRB Intel:  /WR
Motorola:  /RW
  14 D7 D7 NC No
6 E-RDB Intel:  /RD
Motorola:  E
  15 NC No
7 D0 D0 SCLK Serial Clock
  16 VDD Logic power
supply (3.3V)
VDD Logic power
supply (3.3 V)
8 D1 D1 SDIN Serial Data
  17 VLL OLED power
supply (12 V)
VLL OLED power
supply (12 V)
9 D2 D2 NC No
  18 VSS Ground VSS Ground
Typical pinout of the Pictiva displays.
Note:  For the 80x48 version (e.g.OS080048PK09MY0AXX) the connector appears to be "mirrored" as compared to the other versions - see below.

Comment:  It is appears that the presence of a jumper in the "JP1" position will determine if it's a serial or parallel version (e.g.. serial if present, parallel if absent.)

Identifying pin 1:

For the 128x64 unit above, pin 1 is that pin which is on the far right side when the facing the active area of the display with the connector above the display module itself, as oriented in this picture.

Suitable connectors:

It should go without saying that the 0.5 mm (Yes, half-millimeter!) pitch is not hobbyist-friendly, but with care one may interface to it.  The use of a connector is strongly recommended and usable connectors include the Hirose FH12A-18S-0.5SH (Digi-Key P/N:  HFK18CT-ND) and the Omron  XF2H-1815-1 (Digi-Key P/N:  OR643CT-ND) - but there are others!

The picture linked above shows a connector interfaced with "flying leads" (#30 wire wrap) and stabilized with epoxy to provide a more "friendly" interface to the rest of the world.  Of course, better option would be to make a small circuit board that provided a DIP form factor: If you make some, please let me know - or better yet, throw a couple of them my way:-)

Important note concerning the 80x48 display:  It would appear, but has not been positively verified, that the pins are mirrored (e.g. pin 1 on the 128x64 display corresponds, with pin 18 on the 80x48, etc.)  This would appear to be because that the orientation of the connector is pointing down instead of up for this display.

Because it is possible to destroy the display with the application of the wrong voltage or through an incorrect pinout, please do your own research to determine the proper pin configuration and to verify that you have connected to the pins in a reliable manner.  Do not connect/disconnect the display from the connector with power applied!

Description of the I/O pins:

Depending on the literature and/or product, some of these pins may have alternate names as noted in [square brackets.]  Both names are noted below in the description.

CS1B  [CS#] Chip select.  0 = enabled, 1 = communications disabled
RSTB  [RES#] Chip reset.  0 = reset, 1 = normal operation
C86 (parallel version only)  0 = 6800 ("Motorola"), 1 = 8080 ("Intel") interfacing - see RW-WRB and E-RDB pins (below)
RS (A0)  [D/C#] Data/command select. 0 = Input data is applied to the command register, 1 = Input data is applied to the display memory
RW-WRB (parallel version only) For 6800:  0 = Write, 1 = Read.  For 8080:  Write is initiated if this pin is 0
E-RDB (parallel version only) For 6800:  1 = Read/Write operation permitted.  For 8080:  0 = Read
D0-D7 (parallel version only) Parallel input data.  This devices does NOT have a "4 bit" mode like many LCD displays.  The minimum cycle time (of the chip select line) is 300 ns, a minimum low period of 120 ns, and a minimum high period of 60 ns.  The minimum write data setup time is 40 ns and the access time (for reading) is at least 140 ns.
SCLK (serial version only) Serial clock input.  The maximum clock rate is 4 MHz with a minimum high or low period of 100 ns.
SDIN (serial version only) Serial data input.  Data is latched on the rising edge of the clock and is sent MSB (most significant bit) first.  The minimum setup/hold time is 100 ns.
VDD Logic supply voltage.  This may be as low as 2.4 volts but no more than 3.5 volts, with 2.7 volts being typical.
VCC OLED display voltage.  This may be as low as 8 volts but no more than 16 volts.  If the voltage is below 8-10 volts, it is possible that maximum brightness may not be attained and that the brightness may vary with supply voltage and device temperature.  (Low VCC voltage will not harm the device.)

Parallel data read/write procedure (6800 mode - C86 = 0):

Parallel data read/write procedure (8080 mode - C86 = 1):


Serial data write procedure - Note:  It is not possible to read data or commands from the display when using the serial mode!


Display data:

A byte sent as display data will appear on the display in the location pointed to by the column/row address pointers.

Note that each byte of display data contains data for two pixels:  The lower nybble will contain data for the pixel in column "n" while the upper nybble will contain data for the pixel in column "n+1" with the value in each pixel correlating with the gray scale brightness of 0-15.

After sending the data byte, the column/row pointers will be incremented as necessary, according to the settings in the Set Column Addr. and Set Row Addr. commands.

Display layout:

Internally, the display's RAM is laid out 64 bytes across, which correlates with 128 columns or (called "SEG" or "segments") with 2 pixels per byte in the "x" direction,  and 80 pixels bytes down (called "COM" or "common drivers") vertically in rows.

When illuminating the display pixels, they are "scanned" across each row, one column at a time, moving to the next row down.  (This scanning can be visually demonstrated by setting the "Clock Divide/Freq" command, A3h, to a very slow clock speed and a large divide ratio.  Note that operating for extended periods at extremely slow update speeds may reduce the lifetime of the display.)

Of course, not all of this display memory may be used:  For the 128x64 display, all 64 column bytes are used horizontally, but the memory "below" row 63 (the 64th row) is unused and anything written to it will not be displayed:  It may be possible to use this unused display memory for general-purpose RAM - at least if you are using a parallel interface and can read the memory.

Display commands:

The power-up defaults - not all of which are suitable for normal operation - are noted in [square brackets.]
(D/C line = 0)
15, x1, x2 3 Set Column Addr. Bits 0-5 of x1 sets the column start address, x2 sets the column end address (0-3Fh) Note that there are two pixels per byte [Default = 0]
75, y1, y2 3 Set Row Addr. Bits 0-6 of y1 sets the row start address, y2 sets the row end address (0-4Fh) [Default = 0]
81, x 2 Set contrast register Bits 0-6 (0-79h)  Higher value = higher contrast [Default = 0]
84 1 Quarter current range Maximum current per segment is 1/4 of maximum [Default]  Note:  Commands 84h, 85h, and 86h select different current ranges and only one of these three settings may be in effect at any given instant.
85 1 Half current range Maximum current per segment is 1/2 of maximum
86 1 Full current range Maximum current per segment is available
A0, x 2 Set Re-mapping Bits 0-6 of x set mapping as follows:
Bit 0:  0 = disable column address remap, 1= enable [Default = 0]
Bit 1:  0 = Disable nybble remap, 1 = enable [Default = 0]
Bit 2:  0 = Horizontal address increment, 1 = Vertical address increment [Default = 0]
Bit 3:  (reserved)
Bit 4:  0 = Disable COM remap, 1 = enable [Default = 0]
Bit 5:  (reserved)
Bit 6:  0 = Disable COM split Odd/Even, 1 = enable [Default = 0]
A1, x 2 Set display start line Bits 0-6 of x set display RAM start line, 0-79d [Default = 0]
A2, x 2 Set Display offset Bits 0-6 of x set vertical scroll by COM, 0-79d [Default = 0]
A4 1 Normal Display mode Normal display:  Light segments on dark background [Default] This overrides commands A5h, A6h and A7h.
A5 1 Entire display on All pixels turned on and set to GS level 15.  To restore operation, one must send command A4h.
A6 1 Entire display off All pixels turned off.  To restore normal operation, one must send command A4h.
A7 1 Inverse display Display is inverted in brightness (e.g. as in a film "negative")
A8, x 2 Set Multiplex ratio Bits 0-6 of x set multiplex ratio.  Valid range is 10h to 4Fh [Default = 4Fh]
AD, x 2 Set DC-DC converter x = 03h - enable DC-DC converter [Default] x = 02 - disable DC-DC converter (not used on the 80x96 and 80x128 Pictiva displays)
AE 1 Display off Turns off display, puts in power-saving mode [Default]  This command compliments AFh.
AF 1 Display on Turns on display.  This command MUST be invoked before attempting to send other commands/displaying anything.  This command compliments AEh.
B1, x 2 Set phase length Bits 0-3 of x sets the P1 period of the DCLK
Bit 4-7 of x sets the P1 period of the DCLK
[Default = 53h]
B2, x 2 Set row period Bits 0-7 of x set the number of DCLKs per row, valid values being 2-9Eh.  [Default = 25h]
B3, x 2 Set Display Clock Divide ratio/osc. freq. Bits 0-3 of x sets the divide ratio of the oscillator, with values 0-Fh corresponding with ratios from 1 to 10h (1-16 decimal.)
Bits 4-7 of x sets the oscillator frequency, where frequency increases with the value.
[Default = 02h]
B8, x1..x8 9 Set gray scale table This commands loads an 8-byte table with each byte containing two entries correlating with the gray scale level as follows:

[Default entries for all gray scale levels - except 0 - is 1]

x1 - Bits 0-2 set the gray scale level for brightness level 1 while bits 4-6 are unused.  Note:  Brightness level 0 is ALWAYS zero and cannot be set.
x2 - Bits 0-2 set the gray scale for brightness level 2 while bits 4-6 sets the gray scale for brightness levels 3.
x3 - Bits 0-2 set the gray scale for brightness level 4 while bits 4-6 sets the gray scale for brightness levels 5, etc.
x4...x8 - Gray scale for brightness levels 5-15.
Note that this command requires that all bytes be sent!

BC, x 2 Set precharge voltage Bits 0-7 of x set the precharge voltage level.  Valid values are 0-1Fh, plus:
- If bit 7 is set, precharge voltage = VCOMH
- If bits 6 and 7 are 0 and bit 5 is set, precharge voltage = VREF
[Default = 11h]
BE, x 2 Set VCOMH voltage Bits 0-5 of x set the VCOMH voltage.  The valid range is 0-1Fh.  If bit 5 is set, then VCOMH = VREF (bits 0-4 are ignored) [Default = 11h]
BF, x 2 Set Segment Low Bits 0-3 of x set the VSL voltage.  The valid range is 8h-Eh, plus:
x = 2 - VSL connected to VSS
[Default = Eh]
E3 1 NOP No operation.  When using the serial mode, this command must always be sent before setting the chip select line high.

Additional command information:

- Set Column address x1, x2:  The "x1" parameter sets in which column in the display memory the next data byte will be written, while the "x2" parameter sets the highest column address.

After a display byte is written, the column address is internally incremented by one.  If this new value exceeds the "x2" value, the row address is incremented and the column value is reset to the "x1" value.

Remember that since each byte contains two pixels, there are half as many column addresses as column pixels and that each time you write one byte, you affect two pixels!  The pixel at location 0, 0 is in the lower nybble while the upper nybble contains the pixel in the next column.

Using this command and the "Set Row Address" command you can limit access to just a portion of the display - see below.

- Set Row address y1, y2:  The "y1" parameter sets in which row in the display memory the next data byte will be written, while the "y2" parameter sets the highest row address.

After a display byte is written, the column address is incremented by one, but if this column address exceeds that on the "x2" value of the "Set Column Address" command, the column address is reset to the "x1" parameter of the "Set Column Address" command and the Row address is incremented.  If, by incrementing the row address, it exceeds the value in the "y2" parameter of the "Set Row address" command, it is reset to the "x2" value.

As mentioned above, using the "Set Column Address" and "Set Row Address" can limit the boundaries of the accessible portion of the display to a rectangle bounded by x1, y1;  x2, y1;  x2, y2;  and x1, y2.

- Display Re-mapping:  This can be one of the more confusing commands to understand.  Its purpose is to allow the mechanical layout of the driver IC to match the physical layout of a display matrix and minimize complexity of the that layout.  Unfortunately, where the chip's interface pins connect may not always make for the most convenient routing of conductors if one tried to put them in the correct order.  These commands allow some flexibility in the order where these connections will be made.

The default settings of this register are not usable for the 128x64 display (I have not used the other displays to verify their required configuration) but here are two possibilities:

- Set bit 6 (e.g. 40h) to enable COM Split Odd/Even mode.  This will cause the origin (location 0, 0) to be in the lower-left corner of the display

- Set bits 1, 4 and 6 (e.g. 52h) to enable nybble re-mapping, COM remapping, and enabling of COM Split Odd/Even mode.  This will cause the origin (location 0, 0) to be in the upper-left corner of the display.  If this configuration is used, also apply a value of 40h using the "Set Display Offset" command.  This information comes from another user and I have not personally verified it.

- Contrast control and Quarter/Half/Full Current Range:  These set the available segment current output to the display.  The contrast control linearly varies the segment current with a maximum of 300 microamps being available when the Full Current Range mode is selected with a contrast setting of 7Fh.

A recommended starting point is with Full Current Range enabled with the Contrast control set to 33h.

- Set Display Start Line:  When a display has fewer lines than the SSD0323 is capable of, the "top" line may not correlate with the first row in the display memory, so this parameter is used to tell which line is really the "top" line of the display.  On the 128x64 display, the default value of 0 is appropriate.  (This applies to the RAM address and not the physical "COM" line on the chip.)

- Set Display Offset:  This is used in remapping of the display and is used to tell which "COM" line (the rows on the 128x64 display) is really the start line.

The OLED display is physically laid out such that the bottom row of pixels is really COM0 - the first "common" line which means that row 0 is along the bottom of the display.  If, for example, you wanted the top row to be the "first" line, you would set this parameter to 40h, causing the a 64 line offset toward the top.  Note:  If use the example under "Display Remapping" (above) note that the default value if this is fine for position 0,0 being in the bottom-left corner of the display, but it should be set to 40h if 0,0 is to be in the upper-left corner.

- Normal Display Mode, Entire Display On, Entire Display Off, Inverse Display - These commands are used to set the display mode or are for testing the display.  Normal Display Mode causes (with default gray scale level settings) light pixels on a dark background while the Inverse Display mode causes dark pixels on a light background.  The Entire Display On and Entire Display Off may be used to blank or light up the display.  None of these commands affect the data in display memory.  Note:  If you have executed the Entire Display On or Entire Display Off commands, you will not see any display updates until either the Normal Display Mode or the Inverse Display commands have been issued.

- Set Multiplex Ratio - Not much is known about this command - see the lists of settings below.

- Set DC-DC converter.  The SSD0323 has an on-board voltage converter circuit to produce 12 volts from the low voltage supply, allowing a single voltage supply.  Note, however that this particular model of this display does not use this feature (the appropriate inductors/capacitors are missing) so an outboard 8-16 volt supply is required.  The converter should be commanded off [default] to minimize current consumption.

- Display Off, Display On - The Display Off command (power-up default) puts the display in its minimum power mode and turns it off.  Note that before displaying anything, the Display On command must be sent!

- Set Phase Length - The driving signals for the OLED pixels consist of three phases:  The "Off" (or "P1") phase where no voltage is applied, the "Precharge" (or "P2") phase where a voltage is applied that is just below the threshold of illumination, and the "On" (or "P3") phase where the current drive (set according to the "Quarter/Half/Full current range" command) is applied.  Because the OLED is highly capacitive, the "Precharge" phase allows a faster response to changes in current by minimizing the amount of voltage change on the display.  The "P1" and "P2" parameters should be no longer than necessary to be able to "swing" the voltage on each segment.  The duration of the the "P3" cycle effectively sets the duty cycle of the drive pulse width and is used to set the brightness of each pixel.  More information is below.

- Set Row Length - The OLED has an onboard oscillator and this parameter indicates how many clock periods are to be "spent" on each row.  This parameter also limits what the total of the "P1", "P2" and "P3" periods (plus grayscale setting) may be:  Setting this longer than the maximum required total clock periods  for the maximum brightness level (typically "GS15") will simply slow down the refresh rate (scanning) of the display.

- Set Display Clock Divide ratio/osc. frequency - This controls the effective period of the display's multiplex clock.  The power-up defaults are adequate for general use.

- Set Grayscale Table - This commands the loading of 8 bytes of data containing "GS1" through "GS15."  Note:  Because Gray Scale level 0 is always 0, it cannot be changed.  Note also that the first adjustable gray scale setting (1) is in the lower 3 bits of the byte and that the upper bits are not used and that the other corresponding gray scale settings are in organized slightly differently!

The brightness of a pixel is set using grayscale levels 0-15, with level "0" always being black (off.)  Because the brightness corresponds with the duration of the "P3" period (see above) there are some fixed values associated with each grayscale brightness as follows:

The corresponding value in the Grayscale table is added on to the period above.  Because the power-on default value of each entry of the grayscale table is 1, the total P3 periods for each of the Gray Scale values above is actually one count higher, e.g. 1, 3, 5, 7. etc for Gray levels 1, 2, 3, 4, etc.   Using this command, one may increase the brightness of any individual grayscale level, but not decrease it.  Again, the total of P1, P2, and P3 (plus the above value) CANNOT exceed the value set in the Set Phase Length command, above.

- Set Precharge Voltage - As mentioned above, the the "P2" phase (called the "Precharge" phase) charges the capacitive OLED pixel to a voltage just below that where the pixel starts to illuminate.  If this is set too high, pixels that were supposed to be dimmer (those not set to Gray Scale level 0) will start to light up and contrast will be reduced.  If this is set too low, the opposite will happen and the dimmer pixels may not illuminate as brightly as expected.  An additional possible consequence of improper setting of this parameter is that the brightness of pixels across the display may not be as uniform as it should be.  Note that the voltage at which the OLED pixel starts to illuminate depends somewhat on temperature, so setting of this parameter should take that into account.  This voltage varies from about 50% of Vref (see below) at a setting of 0 to about 80% at a setting of 1Fh.

- Set VCOMH Voltage - The "COM" (common.)  When scanning the display, the "Common" lines (corresponding to the rows of the display) are connected to a positive voltage source - in this case, the "COM" voltage.  This is referenced to the "Vref" voltage which, in the case of this model, is connected to the VCC line.  This parameter sets the "VCOMH" voltage as a ratio of the "Vref" voltage.  This varies from about 50% at a value of 0 to about 80% with a value of 1Fh, with the precise ratio going up when more pixels are illuminated.

This parameter has some effect on how the brightness varies with power supply voltage.  Note that the amount of current available varies with the Quarter/Half/Full Current Range registers, but if the voltage setting is too low for current limiting in the common driver to occur, the higher brightness levels will vary noticeably with power supply voltage.

- Set Segment Low - This is the voltage on the "Seg" (segment) drivers which correspond with the column.  The difference between the "VCOMH" and this parameter effectively set the voltage across each pixel and will affect brightness and contrast somewhat.  Values from 8 to Eh will vary this voltage from approximately 1 to 2 volts (about 0.5 volts higher when many pixels are turned on) and setting a value of 2 will "connect" the segment driver to Vcc (ground.)

Configuration parameters that are known to work:

Empirically, I have determined that the following settings yield a perfectly usable display with good brightness/contrast ratios:

As mentioned above, the "re-map" parameters above set the "origin (the pixel at 0, 0) to be in the Lower Left corner of the display

According to correspondence with another reader, he reports the following parameters suggested by Osram:

In contrast with my empirically-determined parameters, these set the "origin" point (the pixel at 0, 0) to be in the Upper Left corner of the display.

I have yet to try this second set of parameters so I go "on faith" that they work properly.


After playing with the display for a little while, here are some random observations:

A page that shows this display having been used in a homebrew (hobbyist) project is the Using an OLED (Organic LED) display for a pelorus on an RDF system page.

Work continues on this page as time permits.

Again, please make certain that you read the disclaimer at the top of this page!

Do you have any questions on this or other related topics?  Go here.

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This page last updated 20060912

Since 12/2010: